It is well-known that local timing signals in a digital receiver must be synchronized to an incoming digital in order to recover the data. Heretofore, such timing signals were recovered from the incoming digital signal by employing a phase locked loop. The phase locked loop was responsive to the incoming digital signal for generating a phase error signal which, in turn, controls a voltage controlled oscillator to generate a local timing signal.
In frames of certain incoming digital signals, there are additional overhead bit positions and so-called stuffing bit positions which when eliminated leave gaps in the data stream. Because of such gaps, the recovered timing signal generated by a typical phase locked loop arrangement is not smooth causing jitter. As is well-known, jitter is extremely undesirable in timing signals. Additionally, it is desirable that the generated timing signal follow variations in the incoming digital signal caused by the stuffing bits. One arrangement, including compensation for jitter caused by such an incoming signal including gaps is disclosed in U.S. Pat. No. 4,847,875 issued to DooWhan Choi on Jul. 11, 1989. This prior arrangement, however, was limited to using either an analog phase locked loop or to a digital phase locked loop that has a reference time base source frequency which is an integer multiple of the frequency of the output signal from the phase locked loop.
In certain digital transmission systems the readily available "high" frequency reference signals are not necessarily integer multiples of the frequency of the phase locked loop output signal. A desired clock signal could possibly be obtained in such arrangements by employing a frequency synthesizer using fractional division of a reference signal. However, the resulting reference signal would have jitter that would be transferred to the output signal generated by the phase locked loop and the dynamic performance of the loop would not be acceptable or usable in practical applications.